Many available integrated circuits contain large memory arrays. During manufacture of integrated circuits, defects can arise in such memory arrays. It is known that many of these defects, known as “point defects,” prevent function of only a small number of cells. Many other defects, such as row or column defects, can arise in memory arrays and will prevent operation of cells in a particular column or row of the large memory array while permitting operation of other cells in the design.
Memory arrays included in integrated circuits with substantial non-memory function are known herein as embedded memory arrays. Embedded memory arrays include cache memory, such as is often found in processor integrated circuits.
Integrated circuits having unrepaired and/or unbypassed defects in embedded memory arrays are typically of no value in the marketplace. It is desirable to repair and/or bypass defects in embedded memory arrays to improve yield and reduce costs of functional circuits. The larger the percentage of die area occupied by memory arrays, the more likely the array is to have defects.
Many memory arrays available in integrated circuits are equipped with a replacement group of cells intended to be electronically substituted for defective cells in the array; thereby repairing defects in the arrays. These replacement cells may take the form of additional cell rows in an array; these cell rows are accessed in place of rows having defective cells. Replacement cells may also take the form of extra columns in an array; data from these columns is substituted for data from defective columns. Block-organized memories may have entire replacement blocks, where an entire block of defective memory can be substituted with good memory. Replacement cells may also be organized as a small memory having mapping logic for substituting cells of the small memory for defective cells in a larger array. Provision of replacement cells in a memory system is known to significantly improve memory yield, thereby reducing production cost, despite a small die size increase.
With all these techniques, replacement cells must be variably mapped onto the larger memory array of the embedded memory. This mapping requires storage of replacement-cell, column, row, or block mapping information within the integrated circuit. This required replacement-cell, column, row, or block, mapping information is known herein as redundancy information.
It is known that memory defects may be “hard” defects, where cells fail to function under all conditions. Other defects may be speed or temperature related, where cells fail to function only under certain operating conditions. It is therefore desirable to store redundancy information in nonvolatile form within the integrated circuit rather than deriving this information from self-test results at system boot time.
Most integrated circuit processes used for construction of static or dynamic random access memory (SRAM or DRAM) embedded memory arrays do not allow for fabrication of EEPROM or UV-EPROM cells for storage of redundancy information. Storage of redundancy information in nonvolatile form within integrated circuits made on these processes has been accomplished with laser-programmed or fusible link technologies; both types are herein known as programmable links. Laser-programmed links require large die area such that a production machine can locate and program selected links since laser spot size is large compared with line widths obtainable on modern submicron fabrication processes. Fusible-links also require substantial die area for each fusible link, since each link requires associated passivation openings, high-current drivers for fusing the link, and other associated components.
It is therefore desirable to minimize the number of programmable links required to store redundancy information on an integrated circuit.
Many integrated circuits, including processor integrated circuits, contain multiple embedded memory arrays of size sufficiently large that die yields can be improved by providing redundant cells, mapping hardware, and programmable links.
It is common that embedded arrays are organized with a number of columns that is not a power of two. In particular, modern processors often incorporate multiple levels of cache memory, where each cache memory has separate embedded memory arrays for data and for cache tag information. Cache tag information memory arrays are often organized as memory having word length that is not a power of two. Recent processor designs often implement error correction coding (ECC) for cache data memory to protect against soft errors; adding ECC to a memory having word length equal to a power of two generally results in a memory having an internal word length that is not a power of two.